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LTC2255/LTC2254 14-Bit, 125/105Msps Low Power 3V ADCs
FEATURES

DESCRIPTIO
Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 395mW/320mW 72.4dB SNR 88dB SFDR No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 640MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm x 5mm) QFN Package
The LTC(R)2255/LTC2254 are 14-bit 125Msps/105Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2255/ LTC2254 are perfect for demanding imaging and communications applications with AC performance that includes 72.3dB SNR and 85dB SFDR for signals at the Nyquist frequency. DC specs include 1LSB INL (typ), 0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.3 LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation
TYPICAL APPLICATIO
REFH REFL FLEXIBLE REFERENCE
OVDD
SNR (dBFS)
+
ANALOG INPUT INPUT S/H
-
14-BIT PIPELINED ADC CORE
CORRECTION LOGIC
OUTPUT DRIVERS
D13 * * * D0 OGND
CLOCK/DUTY CYCLE CONTROL
22554 TA01a
CLK
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LTC2255: SNR vs Input Frequency, -1dB, 2V Range, 125Msps
75 74 73 72 71 70 69 68 67 66 65 0 50 100 150 200 250 300 350 33554 G09 INPUT FREQUENCY (MHz)
U
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1
LTC2255/LTC2254
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SENSE MODE VCM D13 D12 D11 VDD OF
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... -0.3V to 1V Analog Input Voltage (Note 3) ..... -0.3V to (VDD + 0.3V) Digital Input Voltage .................... -0.3V to (VDD + 0.3V) Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2255C, LTC2254C ............................. 0C to 70C LTC2255I, LTC2254I ...........................-40C to 85C Storage Temperature Range ..................-65C to 125C
ORDER PART NUMBER
24 D10 23 D9 22 D8
32 31 30 29 28 27 26 25 AIN+ 1 AIN- 2 REFH 3 REFH 4 REFL 5 REFL 6 VDD 7 GND 8 9 10 11 12 13 14 15 16
OE D0 D1 D2 D3 CLK SHDN D4
33
21 OVDD 20 OGND 19 D7 18 D6 17 D5
LTC2255CUH LTC2255IUH LTC2254CUH LTC2254IUH QFN PART* MARKING 2255 2254
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 33) IS GND MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
LTC2255 TYP MAX 1 0.5 2 0.5 10 30 5 1.3 5 1 12 2.5
MIN 14 -5.5 -1 -12 -2.5
LTC2254 TYP MAX 1 0.5 2 0.5 10 30 5 1.3 5.5 1 12 2.5
UNITS Bits LSB LSB mV %FS V/C ppm/C ppm/C LSBRMS
14 -5 -1 -12 -2.5
Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference

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LTC2255/LTC2254
A ALOG I PUT
SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS 2.85V < VDD < 3.4V (Note 7) Differential Input (Note 7) 0V < AIN+, AIN- < VDD 0V < SENSE < 1V

Analog Input Range (AIN+ -AIN-) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage MODE Pin Leakage Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth
DY A IC ACCURACY
SYMBOL SNR PARAMETER Signal-to-Noise Ratio
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input IMD Intermodulation Distortion fIN1 = 28.2MHz fIN2 = 26.8MHz

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WU
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MIN 1 -1 -3 -3
TYP 1.5
MAX 1.9 1 3 3
UNITS V V A A A ns psRMS dB MHz
0.5V to 1V
0 0.2 80 Figure 8 Test Circuit 640
MIN
LTC2255 TYP MAX 72.4 72.3
MIN
LTC2254 TYP MAX 72.5 72.4
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
68.9
72.1 71.7 88 85
69.4
72.3 71.7 88 88
73
82 78 90 90
71
84 80 90 90
77
90 90 72.2 72
79
90 90 72.4 72.2
68
71.9 70.2 85
68.5
72 70.6 85
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LTC2255/LTC2254
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V LOGIC INPUTS (CLK, OE, SHDN)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN

POWER REQUIRE E TS
SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power Nap Mode Power
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 8)
CONDITIONS (Note 9) (Note 9)

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(Note 4)
MIN 1.475 TYP 1.500 25 3 4 MAX 1.525 UNITS V ppm/C mV/V
2.85V < VDD < 3.4V -1mA < IOUT < 1mA
TYP
MAX
UNITS V
2 0.8 -10 3 10
V A pF
VIN = 0V to VDD (Note 7)
OE = High (Note 7) VOUT = 0V VOUT = 3V IO = -10A IO = -200A IO = 10A IO = 1.6mA

3 50 50 2.7 2.995 2.99 0.005 0.09 2.49 0.09 1.79 0.09 0.4
pF mA mA V V V V V V V V
MIN 2.85 0.5
LTC2255 TYP MAX 3 3 132 395 2 15 3.4 3.6 156 468
MIN 2.85 0.5
LTC2254 TYP MAX 3 3 107 320 2 15 3.4 3.6 126 378
UNITS V V mA mW mW mW
SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK
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LTC2255/LTC2254
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL fs tL PARAMETER Sampling Frequency CLK Low Time CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7)

TI I G CHARACTERISTICS
tH
tAP tD
Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted.
UW
MIN 1 3.8 3 3.8 3
LTC2255 TYP MAX 125 4 4 4 4 0 500 500 500 500
MIN 1 4.5 3 4.5 3
LTC2254 TYP MAX 105 4.76 4.76 4.76 4.76 0 500 500 500 500
UNITS MHz ns ns ns ns ns
CLK High Time
Sample-and-Hold Aperture Delay CLK to DATA delay Data Access Time After OE BUS Relinquish Time CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7)

1.4
2.7 4.3 3.3 5
5.4 10 8.5
1.4
2.7 4.3 3.3 5
5.4 10 8.5
ns ns ns Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254), input range = 1VP-P with differential drive. Note 9: Recommended operating conditions.
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LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2255: Typical INL, 2V Range, 125Msps
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 CODE 12288 16384
22554 G01
AMPLITUDE (dB)
LTC2255: 8192 Point FFT, fIN = 30MHz, -1dB, 2V Range, 125Msps
0 -10 -20 -30
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60
22554 G04
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60
22554 G05
AMPLITUDE (dB)
LTC2255: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, -1dB, 2V Range, 125Msps
0 -10 -20 -30
AMPLITUDE (dB)
-40
SNR (dBFS)
COUNT
-50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60
22554 G07
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LTC2255: Typical DNL, 2V Range, 125Msps
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16384
22554 G02
LTC2255: 8192 Point FFT, fIN = 5MHz, -1dB, 2V Range, 125Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60
22554 G03
LTC2255: 8192 Point FFT, fIN = 70MHz, -1dB, 2V Range, 125Msps
0 -10 -20 -30 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
LTC2255: 8192 Point FFT, fIN = 140MHz, -1dB, 2V Range, 125Msps
0
10
20 30 40 FREQUENCY (MHz)
50
60
22554 G06
LTC2255: Grounded Input Histogram, 125Msps
25000 20331 18639 75 74 73 72 15000 11975 10000 6939 5000 3684 704 3 79 8181 8183 8185 8187 CODE 2727 419 26 1 8189 8191
22554 G08
LTC2255: SNR vs Input Frequency, -1dB, 2V Range, 125Msps
20000
71 70 69 68 67 66 65 0 50 100 150 200 250 300 350 33554 G09 INPUT FREQUENCY (MHz)
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LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2255: SFDR vs Input Frequency, -1dB, 2V Range, 125Msps
100 95 SNR AND SFDR (dBFS) 90
SNR (dBc AND dBFS)
SFDR (dBRS)
85 80 75 70 65 0 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G10
LTC2255: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
110 100 90 dBFS 145 140 135 130
SFDR (dBc AND dBFS)
80
IVDD (mA)
70 60 50 40 30 20 10 0 -80 -70 -60 -50 -40 -30 -20 -10 0 22554 G14 INPUT LEVEL (dBFS) dBc
LTC2255: IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB, OVDD = 1.8V
8 7 6
SNR (dBFS)
IOVDD (mA)
5 4 3 2 1 0 0 20 40 80 100 60 SAMPLE RATE (Msps) 120 140
22554 G16
UW
LTC2255: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, -1dB
90 SFDR 80 SNR 70
80 70 60 50
LTC2255: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
dBFS
dBc 40 30 20 10
60
50 0 20 40 60 80 100 120 140 160 22554 G11 SAMPLE RATE (Msps)
0 -70
-60
-50
-40 -30 -20 INPUT LEVEL (dBFS)
-10
0
22554 G13
LTC2255: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
125 120 115 110 105 100 95 0 20 60 80 100 40 SAMPLE RATE (Msps) 120 140
22554 G15
2V RANGE 1V RANGE
LTC2255: SNR vs SENSE, fIN = 5MHz, -1dB
74 73 72 71 70 69 68 67 66 65 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1
22554 G32
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LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2254: Typical INL, 2V Range, 105Msps
2.0 1.5 1.0
DNL ERROR (LSB)
INL ERROR (LSB)
AMPLITUDE (dB)
0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 CODE 12288 16384
22554 G17
LTC2254: 8192 Point FFT, fIN = 30MHz, -1dB, 2V Range, 105Msps
0 -10 -20 -30 0 -10 -20 -30
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 30 40 20 FREQUENCY (MHz) 50
22554 G20
LTC2254: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, -1dB, 2V Range, 105Msps
0 -10 -20 -30
AMPLITUDE (dB)
-40 -60 -70 -80 -90 -100 -110 -120 0 10 30 40 20 FREQUENCY (MHz) 50
22554 G23
COUNT
-50
12000 10000 8000 6000 4000 2000 0
11299
SNR (dBFS)
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LTC2254: Typical DNL, 2V Range, 105Msps
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4096 8192 CODE 12288 16384
22554 G018
LTC2254: 8192 Point FFT, fIN = 5MHz, -1dB, 2V Range, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 30 40 20 FREQUENCY (MHz) 50
22554 G19
LTC2254: 8192 Point FFT, fIN = 70MHz, -1dB, 2V Range, 105Msps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 10 30 40 20 FREQUENCY (MHz) 50
22554 G21
LTC2254: 8192 Point FFT, fIN = 140MHz, -1dB, 2V Range, 105Msps
-40 -50 -60 -70 -80 -90 -100 -110 -120
-120
0
10
30 40 20 FREQUENCY (MHz)
50
22554 G22
LTC2254: Grounded Input Histogram, 105Msps
20000 18000 16000 14000 10516 17646 18027
75 74 73 72 71 70 69 68
LTC2254: SNR vs Input Frequency, -1dB, 2V Range, 105Msps
3380 3 54 581 8183 8185 8187 8189 CODE
3316 637 68 1 8191 8193
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67 66 65 0 50 100 150 200 250 300 350 33554 G25 INPUT FREQUENCY (MHz)
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LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS
LTC2254: SFDR vs Input Frequency, -1dB, 2V Range, 105Msps
100 95
SNR AND SFDR (dBFS)
90 SFDR
90
SFDR (dBRS)
SNR (dBc AND dBFS)
85 80 75 70 65 0 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G26
LTC2254: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps
110 100 90
SFDR (dBc AND dBFS)
80 70 60 50 40 30 20 10 0 -80 -70 -60 -50 -40 -30 -20 -10 0 22554 G29 INPUT LEVEL (dBFS)
85 80 75 0 20 40 60 80 SAMPLE RATE (Msps) 100 120
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IVDD (mA)
LTC2254: IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB, OVDD = 1.8V
7 6 5 SNR (dBFS) IOVDD (mA) 4 3 2 1 0 0 20 60 80 40 SAMPLE RATE (Msps) 100 120
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dBc
LTC2254: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, -1dB
80 70 60 50
LTC2254: SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps
dBFS
80 SNR 70
dBc 40 30 20 10
60
50 0 20 40 60 80 100 SAMPLE RATE (Msps) 120 140
22554 G27
0 -70
-60
-50
-40 -30 -20 INPUT LEVEL (dBFS)
-10
0
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LTC2254: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
120 115 110 105 100 95 90 2V RANGE 1V RANGE
dBFS
LTC2254: SNR vs SENSE, fIN = 5MHz, -1dB
74 73 72 71 70 69 68 67 66 65 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1
22554 G33
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LTC2255/LTC2254
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1F ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2F ceramic chip capacitor and to ground with a 1F ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1F ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2F ceramic chip capacitor and to ground with a 1F ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. D0 - D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D13 is the MSB. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor. OVDD can be 0.5V to 3.6V. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. VDD selects 2's complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a 0.5V input range. VDD selects the internal reference and a 1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of VSENSE. 1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2F ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.
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LTC2255/LTC2254
FUNCTIONAL BLOCK DIAGRA
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE AIN-
VCM 2.2F
1.5V REFERENCE
RANGE SELECT
REFH SENSE REF BUF
DIFF REF AMP
REFH
0.1F
2.2F 1F 1F
Figure 1. Functional Block Diagram
TI I G DIAGRA
tAP ANALOG INPUT N tH tL CLK tD D0-D13, OF N-5 N-4 N-3 N-2 N-1 N
22554 TD01
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SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D13 CONTROL LOGIC OUTPUT DRIVERS * * * D0 REFL CLK M0DE SHDN OE
22554 BD01
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OGND
Timing Diagram
N+2 N+3
N+4 N+5
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log ((V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2255/LTC2254 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2255/LTC2254 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and
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input tone to the RMS value of the largest 3rd order intermodulation product.
W
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2255/ LTC2254 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed
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to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.
LTC2255/LTC2254 VDD 15 AIN+ VDD 15 CPARASITIC 1pF VDD CLK CPARASITIC 1pF CSAMPLE 3.5pF CSAMPLE 3.5pF AIN-
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Figure 2. Equivalent Input Circuit
Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN- should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing 0.5V for the 2V range or 0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2F or greater capacitor.
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2255/LTC2254 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2255/LTC2254 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100 for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.
ANALOG INPUT
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Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25 resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.
VCM 2.2F 0.1F ANALOG INPUT T1 1:1 25 25 T1 = MA/COM ETC1-1T 25 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN-
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25 0.1F
AIN+
LTC2255/ LTC2254
12pF
Figure 3. Single-Ended to Differential Conversion Using a Transformer
VCM HIGH SPEED DIFFERENTIAL 25 AMPLIFIER 2.2F AIN+ LTC2255/ LTC2254
+
CM
+
12pF
-
-
25 AIN-
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Figure 4. Differential Drive with an Amplifier
VCM 1k 0.1F ANALOG INPUT 1k 25 2.2F AIN+
LTC2255/ LTC2254
12pF 25 0.1F AIN-
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Figure 5. Single-Ended Drive
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.
VCM 2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 12 AIN-
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12 0.1F
AIN+
LTC2255/ LTC2254
8pF
T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz
VCM 2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN-
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AIN+ 0.1F LTC2255/ LTC2254
1.5V VCM 2.2F
Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz
VCM 2.2F 0.1F ANALOG INPUT 25 T1 0.1F 25 8.2nH
-
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8.2nH 0.1F
AIN+
LTC2255/ LTC2254
AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE
Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz
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Reference Operation Figure 9 shows the LTC2255/LTC2254 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (1V differential) or 1V (0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output
LTC2255/LTC2254 4 1.5V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 * VSENSE FOR 0.5V < VSENSE < 1V 1F 2.2F 0.1F DIFF AMP 1F REFL INTERNAL ADC LOW REFERENCE
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Figure 9. Equivalent Reference Circuit
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor.
1.5V VCM 2.2F 12k 0.75V 12k SENSE 1F LTC2255/ LTC2254
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Figure 10. 1.5V Range ADC
Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.7dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11). The noise performance of the LTC2255/LTC2254 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.
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4.7F FERRITE BEAD 0.1F SINUSOIDAL CLOCK INPUT 0.1F 1k CLK 50 1k NC7SVU04 LTC2255/ LTC2254 CLEAN SUPPLY
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Figure 11. Sinusoidal Single-Ended CLK Drive
Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large
CLEAN SUPPLY FERRITE BEAD 0.1F
4.7F
CLK 100
LTC2255/ LTC2254
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IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
ETC1-1T 5pF-30pF DIFFERENTIAL CLOCK INPUT
CLK
LTC2255/ LTC2254
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0.1F
FERRITE BEAD VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2255/LTC2254 is 125Msps (LTC2255) and 105Msps (LTC2254). The lower limit of the LTC2255/LTC2254 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2255/LTC2254 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will
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require a hundred clock cycles for the PLL to lock onto the input clock. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V Range) >+1.000000V +0.999878V +0.999756V +0.000122V 0.000000V -0.000122V -0.000244V -0.999878V -1.000000V <-1.000000V OF 1 0 0 0 0 0 0 0 0 1 D13 - D0 (Offset Binary) 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 D13 - D0 (2's Complement) 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000
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Digital Output Buffers Figure 14 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external
LTC2255/LTC2254 OVDD VDD VDD 0.5V TO 3.6V 0.1F OVDD DATA FROM LATCH OE OGND PREDRIVER LOGIC 43 TYPICAL DATA OUTPUT
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Figure 14. Digital Output Buffer
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2255/LTC2254 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format Using the MODE pin, the LTC2255/LTC2254 parallel digital output can be selected for offset binary or 2's complement format. Connecting MODE to GND or 1/3V DD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2's complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.
Table 2. MODE Pin Function
MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2's Complement 2's Complement Clock Duty Cycle Stablizer Off On On Off
Overflow Bit When OF outputs a logic high the converter is either overranged or underranged. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up
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to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state. Grounding and Bypassing The LTC2255/LTC2254 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1F capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2F capacitor between REFH and REFL can be somewhat
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LTC2255/LTC2254
APPLICATIO S I FOR ATIO
further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2255/LTC2254 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2255/LTC2254 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz. In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.
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The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply. For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
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R4 24.9 25 48 C4 0.1F 1 OE1 VCC RN1D 33 RN1C 33 RN1B 33 RN1A 33 RN2D 33 RN2C 33 RN2B 33 RN2A 33 RN3D 33 RN3C 33 RN3B 33 RN3A 33 RN4D 33 RN4C 33 RN4B 33 RN4A 33 C17 0.1F VCC R11 10k 8 7 NC7SV86P5X 1 2 4 6 C26 10F 6.3V C20 0.1F R14 1k 3 5 7 GND 8 1/3VDD 2/3VDD R15 1k VDD VCC LT1763 R17 105k R18 100k VDD VDD E3 GND C27 0.01F C28 1F E2 VDD 3V 1 8 IN OUT 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN C18 0.1F 6 5 R12 10k R13 10k 7 1 2 3 C7 2.2F C8 0.1F 5 6 C9 1F VDD C11 0.1F 8 9 10 VDD VDD 11 GND 32 C14 0.1F VCM 31 C15 2.2F 30 VCC 29 C16 0.1F JP2 OE GND VDD 7 4 R6 12.4 24 OE2 GND 4 LE1 GND 10 LE2 VCC 18 VCC GND
C3 0.1F VCM
R5 50
LTC2255/LTC2254
3201S-40G1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
L1 BEAD
C5 4.7F 6.3V C6 1F
R7 1k
C10 0.1F
J3 CLOCK INPUT
C12 0.1F
NC7SVU04
R8 49.9 C13 0.1F VDD JP1 SHDN VDD
R9 1k
47 I0 46 I1 44 I2 43 I3 41 I4 40 I5 38 I6 37 I7 36 I8 35 I9 33 I10 32 I11 30 I12 29 I13 27 I14 26 I15 2 O0 3 O1 5 O2 6 O3 8 O4 9 O5 11 O6 12 O7 13 O8 14 O9 16 O10 17 O11 19 O12 20 O13 22 O14 23 O15
NC7SVU04 R10 33 33
LTC2255/LTC2254 12 D0 AIN+ 13 D1 AIN- 14 D2 REFH 15 D3 REFH 16 REFL D4 17 REFL D5 18 VDD D6 19 GND D7 22 D8 CLK 23 D9 SHDN 24 OE D10 25 D11 26 D12 27 D13 VDD 28 VCM OF 21 SENSE OVDD 20 MODE OGND GND
JP3 SENSE JP4 MODE VDD
39 39 37 37 35 35 33 33 31 31 29 29 27 27 25 25 23 23 21 21 19 19 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1
VDD
1
VDD
2
VCM
3
VCM
4
24LC025 1 VCC A0 2 WP A1 3 A2 SCL 4 A3 SDA
E1 EXT REF
EXT 5 REF 6
VCC
C19 0.1F R16 1k
C21 0.1F
C22 0.1F
C23 0.1F
C24 0.1F
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C25 4.7F E4 PWR GND
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VDD
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Evaluation Circuit Schematic of the LTC2255/LTC2254
VCC VCC R2 12.4 74VCX16373MTD 34 45 39 42 15 GND GND 21 GND VCC 31 C2 8.2pF GND GND 28 R3 24.9 T1 ETC1-1T 5 1 2 4
J1 ANALOG INPUT
R1 OPT
C1 0.1F
*
*3
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APPLICATIO S I FOR ATIO
Silkscreen Top
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Topside Inner Layer 2 GND
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LTC2255/LTC2254
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Inner Layer 3 Power
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Bottomside Silkscreen Bottom
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LTC2255/LTC2254
PACKAGE DESCRIPTIO
5.50 0.05 4.10 0.05 3.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 0.00 - 0.05
NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.45 0.10 (4-SIDES)
(UH32) QFN 1004
0.200 REF
0.25 0.05 0.50 BSC
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LTC2255/LTC2254
RELATED PARTS
PART NUMBER LTC1747 LTC1748 LTC1749 LTC1750 LT1993 LTC2220 LTC2220-1 LTC2221 LTC2222 LTC2223 LTC2224 LTC2225 LTC2228 LTC2229 LTC2248 LTC2249 LTC2252 LTC2253 LTC2292 LTC2293 LTC2294 LTC2297 LTC2298 LTC2299 LT5512 LT5514 LT5522 DESCRIPTION 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC High Speed Differential Op Amp 12-Bit, 170Msps ADC 12-Bit, 185Msps ADC 12-Bit, 135Msps ADC 12-Bit, 105Msps ADC 12-Bit, 80Msps ADC 12-Bit, 135Msps ADC 12-Bit, 10Msps ADC 12-Bit, 65Msps ADC 12-Bit, 80Msps ADC 14-Bit, 65Msps ADC 14-Bit, 80Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC Dual 12-Bit, 40Msps ADC Dual 12-Bit, 65Msps ADC Dual 12-Bit, 80Msps ADC Dual 14-Bit, 40Msps ADC Dual 14-Bit, 65Msps ADC Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 600MHz BW, 75dBc Distortion at 70MHz 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.5dB SNR, 9mm x 9mm QFN Package 660mW, 67.5dB SNR, 9mm x 9mm QFN Package 475mW, 67.9dB SNR, 7mm x 7mm QFN Package 366mW, 68dB SNR, 7mm x 7mm QFN Package 660mW, 67.5dB SNR, 7mm x 7mm QFN Package 60mW, 71.4dB SNR, 5mm x 5mm QFN Package 210mW, 71dB SNR, 5mm x 5mm QFN Package 230mW, 71.6dB SNR, 5mm x 5mm QFN Package 210mW, 74dB SNR, 5mm x 5mm QFN Package 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 240mW, 71dB SNR, 9mm x 9mm QFN Package 410mW, 71dB SNR, 9mm x 9mm QFN Package 445mW, 70.6dB SNR, 9mm x 9mm QFN Package 240mW, 74dB SNR, 9mm x 9mm QFN Package 410mW, 74dB SNR, 9mm x 9mm QFN Package 445mW, 73dB SNR, 9mm x 9mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports
22554fa
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0306 * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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